1. Field of the Invention
The present invention relates in general to a System-on-a-Chip (SoC), more particularly, to an apparatus and a method for setting a routing path between routers in a chip.
2. Description of the Related Art
To facilitate Internet access or computing functions of digital data equipment like cell phones, PDAs (Personal Digital Assistants), digital TVs, and smart phones, a number of semiconductor chips including a microprocessor, a network chip, and a memory are required. As the data equipment has become more complicated, integration among these products is already occurring and will become a necessity in the near future. If that happens, even more chips will be required within one single data device.
Developed as an answer to the above is a System-on-a-Chip (SoC) technology which integrates features of every component (even semiconductors) on a single chip. In general, the SoC system is constructed of a computing element, input and output (I/O), logic, and memory. The compact and high-integration SoC features high performance and low power consumption, so a majority of data equipment will benefit from the SoC technology. Intellectual property (IP) is also used to help designers to create the semiconductor chip much more rapidly. The IP is a design block that is specially developed as a ready-to-use application to the single chip.
Many studies on the SoC are in progress. In particular, a scheme for connecting IPs built in a chip is considered very important. For example, a bus architecture and a network architecture are currently used to connect IPs. Unfortunately however, the bus architecture already exposed its limit as the amount of data transmitted/received between IPs increases. This is because when a specific IP uses a bus, and other IPs cannot use the bus at all. That is, the bus is exclusively used for the specific IP.
Moreover, the bus architecture is not extendable but fixed, so that additional IPs of the chip cannot be connected to a bus. As an attempt to solve the performance drawback of the bus architecture, the network architecture is devised to connect IPs. The network architecture, compared to the bus structure, consumes less power. Hereinafter, the network architecture for the SoC will be called ‘NoC’ (Network-on-Chip).
FIG. 1 illustrates a chip architecture using n x n net topology according to an embodiment of the present invention. The chip network architecture using n×n net topology will now be explained in detail with reference to FIG. 1. Particularly, FIG. 1 illustrates a 4×4 net topology. As shown in FIG. 1, the NoC includes a plurality of IPs and switches S corresponding to respective IPs. In other words, there is a one-to-one correspondence between the IPs and the switches. Each switch is interconnected to adjacent switches, and receives data from those adjacent switches. If the destination address of the transferred data is identical with the address of a switch, the data is transferred to an IP connected to the switch. However, if the destination address of the transferred data is not identical with the address of the switch, the data is retransmitted back to the adjacent switch.
It is assumed that a switch S5 generates data to be transferred to at least two adjacent switches at a certain point. The data is directly generated by the IP5 or is transferred from adjacent switches. For instance, provided that the switch S5 generates data to be transferred to the switches, S1, S4, S6, and S9, the S5 determines the priority of the data to be transferred to the adjacent switches. A user can change the priority as desired. For example, the priority levels can be designated according to data capacity. For convenience of explanation, it is assumed that the switch S5 determined the priority in order of the S1, S4, S6, and S9. However, it is to be understood that other priorities are possible.
The S5 transfers the data to the adjacent switches according to the priority. That is, the S5 transfers the data to the S1 first since it has the highest priority, and lastly to the S9 having the lowest priority. If there is data which is not transferred in real time mode (that is, low priority data), such data is stored in a buffer of the S5 to prevent the data loss.
Still a problem arises that under the NoC environment, the transmission of 100 packets per buffer is not possible. If the buffer is to transmit 100 packets of data as the existing network does, the buffer size will have to be increased also. If the buffer size increases, the chip size should be increased accordingly, and as a result of this, the SoC loses its own function. Moreover, as the number of IPs constructing one chip increases, the number of data packets being transmitted and received increases as well. The increase in data packets to be transmitted and received also causes problems including an increase in the buffer size, an increase in the complexity of a chip, and delay in data transfer.